The present invention relates in general to random access memory and, more particularly, to a static random access memory (SRAM) with sense amplifiers and latching circuit.
An SRAM is commonly used for storing digital data which can be retrieved and latched at one or more output ports in response to an address signal. When a particular data cell of the SRAM is addressed, a differential data signal of say 100 millivolts (mv) is developed which must be amplified to conventional logic levels for use by other circuitry. This can be achieved with sense amplifiers coupled to the data cell columns for amplifying the low level differential data signal. A first sense amplifier may convert the 100 mv differential data signal from the data cell to a 4.5 volt and 1.5 volt intermediate differential signals, while a second sense amplifier converts the intermediate differential signals to 0.0 volt and 5.0 volt logic levels.
Sense amplifiers in prior art SRAMs consume an appreciable amount of power when active. The power consumption can be unacceptably high in wide-word and multiport applications where a significant number of sense amplifiers are active simultaneously. Therefore, in order to reduce the power consumption, the digital data is latched at the output port of the SRAM and the sense amplifiers are powered down after sensing and amplification are complete. The sense amplifiers are powered down approximately 50% of the read cycle and 100% of the write cycle.
Conventional sense amplifier designs have a problem with read cycle delay following power-down where the first stage sense amplifier outputs end up at voltage levels not compatible with the second stage sense amplifier. When the first stage sense amplifier is powered down, its outputs are weakly driven towards the positive power supply V.sub.DD at different rates. Thus, at the beginning of the read cycle, the voltage levels of the intermediate differential signals at the inputs of the second stage sense amplifier are unknown. The intermediate signal going high (4.5 volts) during the read cycle has less drive capacity and requires more time to transition to steady state than the intermediate signal going low (1.5 volts). Therefore, the transitions to the data signal experience a push-out delay to allow time for the positive going intermediate signal to reach a steady state high (4.5 volts) regardless of its starting position (worse case 0.0 volts). The push-out delay necessary to compensate for the worse case rise time slows the operating speed of the SRAM.
Several types of latching circuits are used in the prior art each with its own disadvantages. One latching circuit is a cross-coupled latch activated by a clock signal a predetermined time after the differential data signal from the memory cell is developed. The latching circuit requires critical timing for the clock signal. If the latch is activated too soon, the data may not be valid yet and incorrect data is latched. Alternately, if the latch is activated too late, the read access time is delayed thereby reducing the overall performance of the SRAM. Another type of latching circuit must be over-driven by the second stage sense amplifier resulting in a delay of the read access time.
Hence, a need exists for an SRAM with a first sense amplifier that does not degrade read performance after power down, and a latching circuit that does not require a critically-timed activation clock or have to be over-driven by the second sense amplifier resulting in a read delay.